This application claims priority to GB Application No. 1010333.1 filed 21 June 2010, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of trace streams generated and analysed so as to assist in the diagnosing the behaviour and the debugging of data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems including tracing circuitry coupled to the processing circuitry and configured to generate a trace data stream indicative of processing operations performed by the processing circuitry. An example of such systems are the integrated circuit designs produced by ARM Limited of Cambridge, England which include a processor core and an embedded trace macrocell (ETM) coupled to the processor core to generate a stream of trace data. This trace data may be buffered on-chip prior to being sent off-chip for analysis. The analysis may utilise a general purpose computer reading the trace data stream and interpreting the trace data stream to reconstruct the processing operations which gave rise to that trace data stream.
The provision of multiple trace streams (e.g. as provided by the CoreSight funnel mechanisms designed by ARM Limited of Cambridge, England), such as, for example, an instruction trace stream and a data trace stream, can have a number of advantages. These include the ability to easily filter between instructions and data. The tracing mechanisms may also be more readily set up to handle instructions and data differently. A trace stream decompressor may be configured to decode the instruction stream and only decode the data stream when necessary. Having a dedicated instruction trace stream and a dedicated data trace stream will also typically reduce the amount of header space required within each stream thereby yielding improvements in bandwidth. The tracing circuitry may employ separate first-in-first-out memories and permit use of disproportionately smaller input stages. The separate instruction trace stream and data trace stream also allows greater flexibility in overflow behaviour, such as permitting a loss of the data trace stream to occur without loss of the instruction trace stream. Furthermore, data trace suppression (i.e. mechanisms to stop generation of trace data relating to data values being processed) need not be explicitly provided since the data trace stream can be ignored if it is not required.